IEC 60747-15 / JEDEC Intermediate Power Semiconductor Reliability & Packaging

IGBT Module Multi-Layer Thermal Foster Network & SOA

Model multi-layer conduction from Silicon Die through DBC ceramic and baseplate to heatsink, tracking T_j ripple.

Solves the 4-stage Foster and Cauer thermal impedance network (Z_th(j-c), Z_th(c-s), Z_th(s-a)) of an industrial IGBT power module. Calculates conduction and switching dissipation, junction temperature ripple ΔT_j, and Safe Operating Area (SOA) thermal limits.

Governing Physical Law & Equations

Z_{th}(t) = \sum_{i=1}^4 R_i \left(1 - e^{-t / \tau_i}\right), \quad T_j(t) = T_a + P_{tot} R_{th(j-a)} + \Delta T_{j,ripple}

Transient thermal impedance multi-exponential summation and junction operating temperature.

Law: Fourier Heat Conduction & Electro-Thermal Network Analogy (JEDEC JESD51) | Standard Reference: IEC 60747-15 / JEDEC JESD51-14 / SEMI G42 (Thermal Test of Power Semiconductor Devices)

Adjustable System Parameters

Parameter	Nominal Value	Dynamic Range	Physical Role
PWM Switching Freq f_sw (f_{sw})	12 kHz	1 to 30 kHz	Carrier modulation frequency determining switching loss
Collector Current I_C (I_C)	90 A	20 to 180 A	RMS load current conducted during ON period
Conduction Duty Cycle D (D)	0.55	0.1 to 0.9	Fraction of PWM period where IGBT conducts
Heatsink Thermal Res R_th (R_{th(s-a)})	0.22 K/W	0.05 to 0.6 K/W	Sink-to-ambient thermal resistance (fan cooling)

Analytical Proof & Derivation

Power dissipation combines conduction loss P_cond = V_{CE,sat}(T_j) I_C D and switching loss P_sw = (E_on + E_off) f_sw. By electro-thermal analogy, heat flux corresponds to current and temperature difference to voltage. The multi-layer packaging (Die → Solder → Al₂O₃/AlN DBC → Baseplate → TIM → Heatsink) is represented by 4 RC poles with time constants τ_i = R_i C_i ranging from milliseconds (die level) to tens of seconds (heatsink). Steady junction temperature is T_j = T_a + P_tot (R_{th(j-c)} + R_{th(c-s)} + R_{th(s-a)}).

Verification Benchmark

1200V / 150A IGBT module benchmark: I_C = 90 A, V_{CE,sat} = 1.75 V, D = 0.55, f_sw = 12 kHz, E_on + E_off = 11 mJ. Total power loss P_tot = (1.75 × 90 × 0.55) + (0.011 × 12000) = 86.6 W + 132.0 W = 218.6 W. With R_{th(j-c)} = 0.18 K/W, R_{th(c-s)} = 0.08 K/W, R_{th(s-a)} = 0.22 K/W (Total R_th = 0.48 K/W) and T_a = 40°C: steady-state T_j = 40 + (218.6 × 0.48) = 144.9°C < 175°C max rating. Thermal margin verified.

Field Engineering Insights

Thermal cycling fatigue (ΔT_j > 60 K per power cycle) is the primary degradation mechanism causing bond-wire lift-off and solder layer delamination in industrial motor drives and wind turbine converters. Keeping T_j < 125°C quadruples power cycling lifetime.