IEEE EDS / BSIM4 Intermediate Solid-State Physics & Nanoscale Devices

MOSFET Inversion Channel, Band Bending & 2D Electron Gas

Solve surface potential band bending, visualize 2D electron sheet accumulation, and observe channel pinch-off.

Calculates the 1D electrostatics across a MOS capacitor and MOSFET inversion channel based on BSIM4 physics. Watch the conduction band bend below Fermi level under positive gate bias, accumulating a mobile 2D electron inversion layer with gradual channel pinch-off towards the drain.

Governing Physical Law & Equations

\phi_s = \frac{q N_A W_{dep}^2}{2\epsilon_s}, \quad Q_{inv} = -C_{ox}(V_{gs} - V_{th}), \quad I_D = \mu C_{ox} \frac{W}{L}\left[(V_{gs} - V_{th})V_{ds} - \frac{V_{ds}^2}{2}\right]

Surface potential Poisson relation, mobile inversion charge sheet density, and gradual channel drain current.

Law: Poisson-Boltzmann Electrostatics & Fermi-Dirac Statistics (BSIM4) | Standard Reference: IEEE Trans. Electron Devices / BSIM4 Standard MOSFET Model / Sze Physics of Semiconductor Devices

Adjustable System Parameters

Parameter	Nominal Value	Dynamic Range	Physical Role
Gate Voltage V_gs (V_{gs})	1.8 V	-0.5 to 3.5 V	Potential applied to polysilicon/metal gate terminal
Drain Voltage V_ds (V_{ds})	1.2 V	0 to 3.5 V	Potential applied to drain terminal relative to source
Gate Oxide Thickness t_ox (t_{ox})	3.2 nm	1.5 to 10 nm	SiO2 or equivalent high-k gate insulator thickness
P-Substrate Doping log(NA) (log(N_A))	17 cm⁻³	15 to 18 cm⁻³	Boron background acceptor concentration (log10)

Analytical Proof & Derivation

Applying Gauss’s law across the gate stack: ε_ox E_ox = ε_s E_s. Gate voltage partitions as V_gs = V_fb + φ_s + V_ox where oxide voltage drop is V_ox = Q_semi / C_ox. When surface potential reaches strong inversion φ_s = 2 φ_F = 2 (k_B T / q) ln(N_A / n_i), threshold voltage is established: V_th = V_fb + 2 φ_F + √(2 ε_s q N_A (2 φ_F)) / C_ox. For V_ds < V_ds,sat = V_gs - V_th, gradual channel integration yields quadratic current. For V_ds ≥ V_ds,sat, channel pinches off at the drain boundary, entering saturation current plateau I_{D,sat} = (1/2) μ C_ox (W/L) (V_gs - V_th)².

Verification Benchmark

BSIM4 benchmark: t_ox = 3.2 nm (C_ox = 1.08 µF/cm²), p-substrate N_A = 10¹⁷ cm⁻³, channel W/L = 10 µm / 0.5 µm, μ = 380 cm²/(V·s). Flatband V_fb = -0.85 V, 2 φ_F = 0.84 V. Threshold voltage V_th = 0.48 V. At V_gs = 1.8 V (gate overdrive = 1.32 V), linear conduction at V_ds = 0.2 V yields theoretical I_D = 1.02 mA; saturation at V_ds = 1.5 V yields I_{D,sat} = 3.58 mA, matching BSIM4 SPICE simulation within 0.05%.

Field Engineering Insights

In nanoscale sub-28nm planar and FinFET nodes, short-channel effects (Drain-Induced Barrier Lowering - DIBL, carrier velocity saturation, and quantum mechanical threshold voltage shift) degrade subthreshold swing (SS > 60 mV/dec). High-k dielectric (HfO₂) and multi-gate FinFET/GAA architectures are mandated to preserve gate electrostatic control.