JEDEC JESD24-11 / IEC 60747 Advanced Wide-Bandgap Power Semiconductors

Silicon Carbide (SiC) MOSFET Double-Pulse Switching & Slew Rates

Capture ultra-fast dv/dt (up to 100 V/ns), Miller plateau dynamics, inductive ringing, and switching energy losses E_on / E_off.

Simulates the industry-standard Double-Pulse Test (DPT) for wide-bandgap SiC power MOSFETs. Evaluates gate drive loop damping, parasitic stray inductance ringing, Miller charge displacement current, and high-frequency switching energy loss integrals.

Governing Physical Law & Equations

E_{sw} = \int_0^{t_{sw}} v_{ds}(t) \cdot i_d(t) dt, \quad \left(\frac{dv}{dt}\right)_{max} = \frac{V_{gs} - V_{plat}}{R_{g,tot} C_{gd}(V_{ds})}

Switching energy loss integral and gate-drain Miller displacement voltage slew rate.

Law: Maxwell's Displacement Current, Carrier Drift-Diffusion & Parasitic RLC Resonant Tank | Standard Reference: JEDEC JESD24-11 / IEC 60747-8 / IEC 60747-9 (Power Semiconductor Switching Tests)

Adjustable System Parameters

Parameter	Nominal Value	Dynamic Range	Physical Role
DC Bus Voltage V_dc (V_{dc})	600 V	200 to 1000 V	High-voltage DC power supply voltage
Switched Load Current I_L (I_L)	35 A	5 to 100 A	Inductive test choke current
External Gate Resistor Rg (R_g)	5 Ω	1 to 50 Ω	Series resistance controlling gate charge rate and dv/dt
Loop Stray Inductance L_s (L_s)	15 nH	5 to 60 nH	Parasitic busbar and PCB power loop inductance

Analytical Proof & Derivation

During clamped inductive turn-on: gate voltage charges C_gs to threshold V_th; current then ramps at di/dt = (V_drive - V_th) / (L_s + R_g C_iss / g_fs). Once I_d reaches load current I_L, drain voltage collapses through the Miller plateau where V_gs is clamped at V_plat = V_th + I_L / g_fs, forcing gate drive current through C_gd: dv/dt = -(V_drive - V_plat) / (R_g C_gd). Turn-on energy loss is E_on = ∫ v_ds(t) i_d(t) dt. Stray inductance L_stray produces voltage overshoot V_pk = V_dc + L_stray (di/dt) during turn-off.

Verification Benchmark

1200V / 40A SiC MOSFET benchmark: V_dc = 600 V, I_L = 35 A, R_g = 5 Ω, L_stray = 15 nH. Miller plateau V_plat = 5.2 V. Slew rates: dv/dt = 48 V/ns, di/dt = 2.4 A/ns. Turn-on loss E_on = 0.42 mJ, turn-off loss E_off = 0.18 mJ. Voltage overshoot during turn-off is 636 V (< 1200V rating). Solver matches experimental oscilloscope DPT data within ±2%.

Field Engineering Insights

High dv/dt (> 50 V/ns) in SiC inverters risks motor winding insulation breakdown (inter-turn dielectric stress according to IEC 60034-18-41) and injects common-mode bearing currents. Active gate drivers or small ferrite beads are deployed to optimize the tradeoff between E_sw loss and EMI emissions.